Semester of Graduation
Fall 2019
Degree
Master of Science (MS)
Department
Division of Electrical and Computer Engineering
Document Type
Thesis
Abstract
Time-to-Digital Converters (TDC) have gained increasing importance in modern implementations of mixed-signal, data-acquisition and processing interfaces and are used to perform high precision time intervals in systems that incorporate Time-of-Flight (ToF) or Time-of-Arrival (ToA) measurements. The linearity of TDCs is very crucial since most Digital Signal Processing (DSP) systems require very linear inputs to achieve high accuracy.
In this work, a TDC has been designed in the 0.5 μm n-well CMOS process that can be used for on-chip integration and in applications requiring high linearity. This TDC used a Dual-Slope-ADC-based architecture for the time-to-digital conversion and consists of the following three main sub-circuits: a time-to-voltage conversion part, an integrating part and digital circuitry. The design is operated with ±2.5V supply voltage and the digital circuitry, consisting of two digital counters and an adder, are operated with a clock frequency of 13MHz. The design of the TDC is discussed and simulated and experimental test results and linearity performance of the fabricated TDC are also presented.
Recommended Citation
Sagoe, Jojoe S., "5-Bit Dual-Slope Analog-to-Digital Converter-Based Time-to-Digital Converter Chip Design in CMOS Technology" (2019). LSU Master's Theses. 5012.
https://repository.lsu.edu/gradschool_theses/5012
Committee Chair
Srivastava, Ashok
DOI
10.31390/gradschool_theses.5012
Included in
Electrical and Electronics Commons, VLSI and Circuits, Embedded and Hardware Systems Commons