Master of Science in Electrical Engineering (MSEE)
Electrical and Computer Engineering
An in-house processing capability is developed in this research for silicon-glass bonding for microfabrication and wafer level chip scale packaging (WLCSP) using a wafer bonder. New masking technology for wet etching of glass to a depth of more than 430 µm is reported in this research work along with development of an anodic bonding process that permits electrical feedthroughs for connections to outside world. Three novel masks were developed in this work for deep wet etching of glass. They were multilayers of metals Mo/Cr/Au (mask 1) and Cr/Au/electroplated Ni (mask 2) both in combination with 20 µm thick AZ® P4620 photoresist and anodically bonded silicon (mask 3). Etch depths greater than 600 µm in glass has been achieved using anodically bonded silicon mask 3 above. It may be currently the only method available to achieve etch depths of 1 mm in glass. Earlier barrier of 300 µm etch depth in glass using multilayer metal mask has effectively been broken in this work with an etch depth of 430 µm achieved using electroplated Ni mask 2) above. A high value of 0.88 for the aspect ratio, defined as the ratio of the vertical etch depth to the lateral etch distance, was achieved using mask 1) above. The problem of etched surface roughness observed in glass with undiluted HF etching has been alleviated by use of a combination of 50:5:1 by volume HF:HCl:HNO3. Etch depths of 355 µm has been achieved in silicon using 45 % KOH solution at 50 °C with 1 µm thick oxide mask. The above etch parameters also resulted in smooth etched mirror like surfaces, sharp edges in etched pits and deep trenches in silicon. The decontaminated etched glass and silicon substrates were aligned in-situ and bonded using an AML 402 wafer bonder. The corner areas of the glass wafer were diced to expose the metal lines permitting electrical communication from the anodically bonded packaged chip to the outside world. The concept of WLCSP using anodic bonding has been developed and demonstrated in this research.
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Upadhyaya, Kailash, "Wafer level chip scale packaging using wafer bonder" (2005). LSU Master's Theses. 3798.
Pratul K. Ajmera