Master of Science in Electrical Engineering (MSEE)
Electrical and Computer Engineering
We report a new architecture for a sigma-delta oversampling analog-to-digital converter (ADC) in which the first order modulator is realized using the floating gate MOSFETs at the input stage of an integrator and the comparator. The first order modulator is designed using an 8 MHz sampling clock frequency and implemented in a standard 1.5µm n-well CMOS process. The decimator is an off-chip sinc-filter and is programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth.
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Kommana, Syam Prasad SBS, "First order sigma-delta modulator of an oversampling ADC design in CMOS using floating gate MOSFETS" (2004). LSU Master's Theses. 3638.