Identifier
etd-08262004-170344
Degree
Master of Science in Electrical Engineering (MSEE)
Department
Electrical and Computer Engineering
Document Type
Thesis
Abstract
We report a new architecture for a sigma-delta oversampling analog-to-digital converter (ADC) in which the first order modulator is realized using the floating gate MOSFETs at the input stage of an integrator and the comparator. The first order modulator is designed using an 8 MHz sampling clock frequency and implemented in a standard 1.5µm n-well CMOS process. The decimator is an off-chip sinc-filter and is programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth.
Date
2004
Document Availability at the Time of Submission
Release the entire work immediately for access worldwide.
Recommended Citation
Kommana, Syam Prasad SBS, "First order sigma-delta modulator of an oversampling ADC design in CMOS using floating gate MOSFETS" (2004). LSU Master's Theses. 3638.
https://repository.lsu.edu/gradschool_theses/3638
Committee Chair
Ashok Srivastava
DOI
10.31390/gradschool_theses.3638