Master of Science (MS)
Electrical and Computer Engineering
This work presents IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling analog-to-digital converter using a built-in current sensor [BICS]. Gate-drain, source-drain, gate-source and gate-substrate bridging faults are injected using fault injection transistors. All the four faults cause varying fault currents and are successfully detected by the BICS at a good operation speed. The BICS have a negligible impact on the performance of the modulator and an external pin is provided to completely cut-off the BICS from the modulator. The modulator was designed and fabricated in 1.5 μm n-well CMOS process. The decimator was designed on Altera's FLEXE20K board using Verilog. The modulator and decimator were assembled together to form a sigma-delta ADC.
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Chamakura, Anand K., "IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling ADC" (2004). LSU Master's Theses. 2428.