## LSU Historical Dissertations and Theses

1996

Dissertation

#### Degree Name

Doctor of Philosophy (PhD)

Gil S. Lee

#### Abstract

The deposition and characterization of the silicon oxide and fluorinated silicon oxide films, as interlevel dielectrics in microelectronics devices, prepared by plasma enhanced chemical vapor deposition at low substrate temperature using $\rm Si\sb2H\sb6$ as silicon precursor are studied. The film deposition is limited by the mass transport regime, resulting in nearly temperature independent deposition rate. The characteristics for the silicon oxide films deposited at 120$\sp\circ$C show that the film etch rate is comparable to that obtained by TEOS-based PECVD at 400$\sp\circ$C and the leakage current is comparable to that of the films deposited at 350$\sp\circ$C with conventional SiH$\sb4$ precursor. It also shows that the as-deposited silicon oxide films have 9.4% increase in the film density compared to the thermal silicon oxide films, resulting in the Si-O-Si bridging bond angle of 138$\sp\circ$. The post-metallization annealing in forming gas ambient at 400$\sp\circ$C rather than post-deposition annealing at high temperatures in N$\sb2$ is the most effective way to reduce both the oxide charge and interface trap densities, especially for devices fabricated on the native oxide-free surface. For the fluorinated silicon oxide film deposition, the optimum gas flow ratio of CF$\sb4$, as fluorine precursor, to $\rm Si\sb2H\sb6$ is observed to be in the range of 8-10. The films deposited at a flow ratio of 10 give the film a dielectric constant of 4.25 which is 12% lower than 4.88 obtained for the fluorine-free silicon oxide films. The addition of fluorine into Si-O network helps not only in reducing the effective oxide charges to as low as 1/6 of the value for the fluorine-free silicon oxide films, but also improves the breakdown property by significantly reducing early failures, resulting in the average dielectric breakdown field strength of 8.91 MV/cm. These films have a strong potential for the use as interlayer dielectric material making available a low temperature and high quality film deposition process for submicron device fabrication in the microelectronics industry.

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