A Horizontally Reconfigurable Architecture for Extended Precision Arithmetic (Parallel Computing, Condition Codes Factoring).
Date of Award
Doctor of Philosophy (PhD)
A special computer for high-precision arithmetic and parallel processing which features an ALU that is dynamically reconfigurable under program control has been designed and a prototype machine constructed. The 256-bit ALU consists of eight 32-bit slices each of which has its own ALU operation code in each microinstruction. The slices can remain logically separated from each other, or can be dynamically connected to either or both of their neighbors under control of a segment control code that is part of each microinstruction. The result is a unique parallel architecture which provides real parallelism to user programs at the instruction level while globally retaining a sequential control structure. Management of parallelism is achieved through a two level hierarchy of condition codes and extended instruction sets to support conditional instruction execution. New types of parallel micro-programming tools introduce a system for reconfiguration management and parallel programming. An assembler, debug simulator, and interactive operating environment have been implemented. An analysis of the instruction times to execute arithmetic operations on the machine show that it will be exceptionally fast for problems in computational number theory and factoring of integers.
Chiarulli, Donald Mark, "A Horizontally Reconfigurable Architecture for Extended Precision Arithmetic (Parallel Computing, Condition Codes Factoring)." (1986). LSU Historical Dissertations and Theses. 4178.