Title

Discovering Barriers to Efficient Execution, Both Obvious and Subtle, Using Instruction-Level Visualization

Document Type

Conference Proceeding

Publication Date

1-1-2014

Abstract

CPU performance is determined by the interaction between available resources, microarchitectural features, the execution of instructions, and by the data. These elements can interact in complex ways, making it difficult for those seeing only aggregate performance numbers, such as miss ratios and issue rates, to determine whether there are reasonable avenues for performance improvement. A technique called instruction-level visualization helps users connect these disparate elements by showing the timing of the execution of individual program instructions. The PSE visualization program enhances instructionlevel visualization by showing which instructions contribute to execution inefficiency in a way that makes it easy to locate dependent instructions and the history of events affecting the instruction. A simple annotation system makes it easy for a user to attach custom information. PSE has been used for microarchitecture research, simulator debugging, and for instructional use.

Publication Source (Journal or Book title)

Proceedings of VPA 2014: 1st Workshop on Visual Performance Analysis - held in conjunction with SC 2014: The International Conference for High Performance Computing, Networking, Storage and Analysis

First Page

36

Last Page

41

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