Identifier

etd-11072009-170319

Degree

Master of Science (MS)

Department

Electrical and Computer Engineering

Document Type

Thesis

Abstract

In this work, a ternary to binary converter circuit is designed in 0.5μm n-well CMOS technology. The circuit takes two inputs corresponding to the ternary bits and gives four outputs, which are the binary equivalent bits of the ternary inputs. The ternary inputs range from (-1,-1)3 to (1,1) 3 which are decimal -4 to 4 and the four binary output bits are the sign bit (SB), most significant bit (MSB), second significant bit (SSB) and the least significant bit (LSB). The ternary inputs (-1, 0 and 1) are represented in terms of voltages of -3V, 0V and 3V. Multiple input floating gate (MIFG) MOSFETS are used in the design of ternary to binary converter. The four circuits to generate the SB, MSB, SSB and LSB outputs are designed separately and then connected together to perform the entire conversion. The MIFG MOSFET takes multiple input signals, which are the ternary inputs in this case and calculates the weighted sum of the inputs. This weighted sum of the inputs is called floating gate voltage and is given as input to the CMOS inverter. The CMOS inverter gives a high or low binary output depending on if the floating gate voltage is higher or lower than the threshold voltage of the CMOS inverter. The circuits are simulated using MOSIS BSIM level 7 model parameters. LEDIT version 13 is used for the layout and a total of 22 transistors are used in the design of the converter circuit. The floating gate of the transistor is simulated by not giving the input directly to the gate of the transistor. Instead inputs are fed to one end of the capacitors and the other end of the capacitors are tied together and given as an input to the inverter. The converter chip occupies an area of 1140 × 2090 μm2.

Date

2009

Document Availability at the Time of Submission

Release the entire work immediately for access worldwide.

Committee Chair

Srivastava, Ashok

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