Identifier

etd-01232006-212520

Degree

Master of Science in Electrical Engineering (MSEE)

Department

Electrical and Computer Engineering

Document Type

Thesis

Abstract

Reconfigurable computing provides a fast and flexible solution for intensive computing processes. Thus, it acts as a bridge between software controlled and hardware based processors. The self–reconfigurable gate array (SRGA) is a reconfigurable architecture that allows fast switching between operations on a reconfigurable device. It consists of a 2-dimensional array of processing elements (PEs) connected using a binary tree structure, called a circuit-switched tree (CST). A CST is a balanced binary tree in which leaves represent processing elements (PE) and internal nodes represent switches. The PEs in the CST communicates with each other by configuring the appropriate switches in the communication path for different types of communication patterns. In this thesis, we have designed and implemented digital blocks for the routing algorithms provided by Roy et al. [RTV04] for right-oriented communication patterns for width-1 and width-w well-nested sets and width-1 multicast sets. We have extended the work and implemented the algorithm for point-to-point, right-oriented, width-w communication sets. Finally, we have introduced a multi-pattern framework, which accommodates different communication patterns. All the designs are synthesized for 0.25-micrometer technology and area, frequency, and power analyses are performed. The results show the behavior of the designs with four, eight, and 16 PEs. The results prove that the proposed framework occupies less area as compared to the sum of the areas occupied by other communication patterns discussed.

Date

2006

Document Availability at the Time of Submission

Release the entire work immediately for access worldwide.

Committee Chair

Jerry L. Trahan

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